Pre-Silicon Validation Engineer

Job Details:Job Description: As a SoC Design Verification Engineer, you will play a pivotal role in ensuring the successful delivery of high-quality integrated System-on-Chip (SoC) designs that meet stringent specifications. Your contributions will directly support Intel's mission to engineer cutting-edge solutions that redefine technology's impact on the world. This role offers the opportunity to collaborate across multidisciplinary teams, driving innovation and solving complex challenges in SoC verification. Your work will be instrumental in shaping Intel's next-generation products, influencing industry trends, and enhancing Intel's reputation for excellence.

Key Responsibilities

• Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and environments to achieve required coverage levels and confirm adherence to microarchitecture specifications.
• Execute verification plans and system simulation models to analyze power, performance, and design functionality, uncovering and resolving bugs.
• Replicate, root cause, and debug issues in the presilicon environment, implementing corrective measures to address failing tests.
• Collaborate with SoC architects, microarchitects, RTL developers, postsilicon engineers, and physical design teams to enhance verification processes for complex architectural and microarchitectural features.
• Document test plans and lead technical reviews of plans and proofs with design and architecture teams.
• Incorporate security validation activities, including regression and debug tests, ensuring comprehensive security coverage.
• Maintain and refine existing functional verification infrastructure and methodologies, driving continuous improvement.
• Absorb learning from post silicon activities, update test plans for missing coverage, and proliferate improvements to future product designs.Qualifications:Minimum Qualifications:
• Bachelor's degree in Electronics Engineering, Computer Engineering, or a related field.
• 10+ years of experience with a Bachelor's degree, 8+ years of experience with a Master's degree, or 7+ years of experience with a PhD.
• Proficiency in SystemVerilog and Universal Verification Methodology (UVM).
• Proven expertise in verification methodologies and strategies, including directed and random test case development.
• Strong debugging capabilities for SoC, fabric, memory subsystems, and protocols such as PCIe or Ethernet.
• Comprehensive knowledge of microarchitecture concepts and advanced computer architecture.
• Experience in emulation and simulation tools for verification, including power and performance analysis.

Preferred Qualifications: