Physical Design Engineer

About the job

Job DescriptionWe are looking for a motivated Physical Design Engineer to join our Renesas team who can work independently with little or no supervision. Our candidate should be able to execute physical design flow (RTL-GDSII & STA) per planned schedule, assess risk and meet all deliverables. Candidate must monitor and drive the program from initiation to tape out, interfacing with internal and external stakeholders and achieve alignment across cross-functional teams.

Responsibilities

• :Drive block level/full chip Place & route and timing closure (Synthesis, PNR, STA and Physical verification)
• .Closely work with mixed signal custom design team on full chip floorplan to integrate analog macro
• sPerform Physical verification DRC, LVS, Antenna & IR-EM checks and fixing error
• sRun timing analysis, debug timing violations and implement functional, timing ECOs and perform formal verification
• .Work on multi-mode and multi-corner timing closure, RC extraction, Cross talk and signoff
• .Work closely with RTL design team to understand design, constraints, clocking and identify issues
• .Setup scan insertion and Integrate DF
• TScript in Tcl/perl to find workaround and solutions to problems and tool issues
• .Customize Synthesis, PNR, STA flows and scripts for various finfet technologies

. Qualificatio

• nsB.Tech or M.Tech in Electronics or Electrical with atleast 2+ years experience in physical design & timing closur
• e.Owned Physical Design and taped out at least a minimum of 1 projects, at least one of them being a first-generation proje
• ctThorough in PD flows, physical verification and multiple tape out experienc
• e.Worked on Synthesis, timing analysis & closure, generating ECO
• s.Experienced in Cadence synthesis, place and route, timing analysis and verification tool
• s.Strong scripting skills - Tcl, perl, csh et
• c.Ability to create methodologies and automate flow
• s.Worked with foundries/IP vendors on tech files, libraries, IP collatera
• lsVery good knowledge of timing libraries, corners/modes, process variations and signal integrity related issues in advanced technology nodes (28nm and belo
• w)Ability to work in a dynamic environment with changing requiremen
• tsTeam player with excellent communication skil
• lsHighly motivated and inspired to continue learning & improving as an individual and as part of a grou

p.