Physical Design Engineer

Job Details:Job Description:

• The Role and Impact
• The HIPD SAM team is responsible for delivering end-to-end Physical Design and Analog Layout for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced testchips for IP and SoC functional blocks. The team supports implementation from RTL/Netlist through GDSII and executes using established Physical Design methodologies and sign-off practices.
• As Physical Design Engineer (Grade 8) By leveraging your expertise, you will directly impact Intel's innovation pipeline, improving product-level parameters such as power, frequency, and area, ensuring our designs deliver exceptional performance and reliability. Join us in driving technology forward and advancing Intel's mission to create world-changing innovation.

Key Responsibilities

• Execute physical design implementation from RTL to GDS, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution.
• Conduct verification and signoff, including formal equivalence verification, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and timing analysis.
• Identify and resolve violations, making recommendations for current and future product architectures.
• Optimize designs to enhance metrics such as power, frequency, and area using industry-standard EDA tools.
• Develop and improve physical design methodologies, automation flows, and processes.
• Possess expertise in structural and physical design, including timing closure, physical clock design, and multiple power domain analysis.
• Define and apply constraints for hierarchical design integration and floor planning concepts.
• Collaborate with cross-functional teams to ensure designs meet Intel's quality and performance standards.Qualifications:Minimum Qualifications
• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 6+ years of relevant experience; or Master's degree in Electrical Engineering, Microelectronics, or VLSI with 4+ years of relevant experience; or PhD with 2+ years of relevant experience.
• Proficiency in RTL-to-GDS flow, including synthesis, placement, routing, and design-for-test using industry-standard EDA tools.
• Advanced knowledge in timing methodology, constraints development, and timing convergence challenges.
• Hands-on experience with low-power designs, multiple power domains, and layout verification.
• Expertise in scripting languages such as Perl, TCL, or Python to enhance automation and design efficiency.