Performance Architect, AI HW

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

The Tensix team is building the high-performance compute fabric that powers Tenstorrent’s AI and ML workloads. As an AI Performance Architect, you will model, analyze, and optimize how real AI workloads run on the Tensix architecture, shaping future hardware features and ensuring every design decision delivers measurable performance gains. This role connects architecture, software, and RTL to push the limits of efficiency and scalability across next-generation AI systems.

This role is hybrid, based out of Toronto, ON; Austin, TX; or remote.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deeply analytical engineer with strong intuition for AI workload behavior and system-level performance bottlenecks.

• Experienced in C++ and Python for simulation, modeling, and performance analysis across heterogeneous compute systems.

• Adept at bridging software and hardware teams—translating deep learning workloads into architectural insight and measurable design tradeoffs.

• Curious, data-driven, and comfortable pushing the limits of efficiency, scalability, and accuracy in high-performance AI systems.

What We Need

• Benchmark and analyze complex AI workloads across single and multi-node hardware configurations to guide next-gen architecture.