Manager, Design Verification

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Role Overview

The Lead Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.

Key Responsibilities

Technical Ownership

Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).

Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.

Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.

Perform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.

Methodology and Automation

Develop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).

Proactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.

Evaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.

Technical Leadership & Team Enablement

Provide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.