Lead STA Engineer

Summary: The Digital Physical Design Engineer is responsible for a physical implementation of IP, Subsystem or IC design.

Job qualification:

• Experience range: 4-7 years

• Should be good in Synthesis Flow setup and Synthesis flows. Should have worked on Genus flows.

• Should be good in STA flow setup and STA flows. Should have worked in Tempus flows.

• Should have worked on STA timing ECOs across multiple technology nodes.

• Should have good understanding in Constraints , clocks.

• Should have excellent communication skills and should be team player.

Job responsibilities:

• The Digital Physical Design Engineer is responsible for a physical implementation of IP, Subsystem or IC design.

• The individual is responsible from RTL synthesis setup , flow cleanup , run multiple experiments to get the best Area , timing and Power , Post-Scan Synthesis netlist STA timing checks , LEC flow setup and cleanup , timing convergence (STA) including related design and timing ECO and should be able to understand the constraints and suggest constraints to Design/DFT teams .

• The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.

More information about NXP in India...