Layout Design Engineer

Job Description: The Role and Impact

• As a Layout Design Engineer, you will be responsible for creating custom layout designs for analog blocks, complex digital and mixed-signal blocks, standard cell libraries, and memory compilers. In this role, you will perform detailed physical array planning, layout optimization, and verification to ensure compliance with design rules and reliability standards. Your work will directly contribute to the development of cutting-edge technologies, enabling innovative products and solutions.
• Business Group
• Join Intel's team focused on advancing silicon design and development for leading-edge technology. This group drives innovation in layout design, ensuring high-quality and efficient solutions that enable Intel's strategic goals. By collaborating with cross-functional teams, the group plays a key role in delivering impactful results for Intel's next-generation technology.
• Key Responsibilities
• - Develop and optimize custom layout designs for analog, digital, and mixed-signal blocks, including memory compilers and standard cell libraries.
• - Perform detailed physical array planning, area optimization, and critical wire analysis.
• - Conduct layout verification, including design rule checks (DRC), layout versus schematic (LVS), and reliability analysis such as electromigration and voltage drop (IR).
• - Utilize custom placement and routing tools to construct high-quality layouts efficiently.
• - Provide feedback to circuit design engineers regarding feasibility studies and implement circuit enhancement requests.
• - Innovate and drive new layout methodologies to improve productivity and ensure design quality.
• - Debug and troubleshoot issues related to layout design, tool flows, and methodologies.

Qualifications:

• Minimum Qualifications
• - Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 0-1 years of hands-on experience in layout design through internships, academic projects, coursework, or hands-on training OR a Master's degree in a relevant field with no prior professional experience.
• - Proficiency in using EDA tools such as Cadence Virtuoso for layout design and verification.
• - Strong understanding of CMOS circuit design concepts and layout principles.
• - Knowledge of layout verification tools like Calibre DRC and ICV.