IR/EM Low Power Design Engineer

About the job

IR/EM Low Power Design Engineer About SemifiveFounded in Seoul in 2019, SEMIFIVE is basing its foundation on Koreas semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVEs core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design, and also provides full turnkey silicon design services for global customers.As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVEs SoC Platform plays a critical role in turning innovative ideas into silicon. SEMIFIVE works closely with global technology leaders and is rapidly emerging as The New Global Hub of Custom Silicon.Semifive India Design Centre, headquartered in Bangalore, is a rapidly growing capability centre responsible for delivering complex, multi-node SoC programs for global customers across the US, Europe, and Asia. The India team owns RTL-to-GDS execution, including physical implementation, timing, power, and signoff for turnkey silicon programs. Job SummaryWe are seeking a highly skilled IR/EM Low Power Design Engineer responsible for analyzing, optimizing, and ensuring power integrity and electromigration reliability in advanced semiconductor designs. The candidate will work closely with physical design, power architecture, and sign-off teams to deliver robust, low-power, high-performance SoC/ASIC designs. Experience1-3 YearsKey Responsibilities Power Integrity & Reliability

• Perform IR Drop (Static & Dynamic) analysis to ensure robust power delivery across the chip.
• Perform Electromigration (EM) analysis to verify current density reliability of power and signal routing.
• Identify power grid weaknesses and recommend design fixes to meet sign-off criteria.
• Develop mitigation strategies including power grid strengthening, decap insertion, and routing optimization.Low Power Design Implementation
• Collaborate with architecture and RTL teams to implement low-power techniques such as:
• Multi-voltage domain design
• Power gating
• Clock gating
• Dynamic voltage and frequency scaling (DVFS)
• Analyze power consumption and optimize switching activity.Physical Design Collaboration
• Work closely with floorplanning and place & route teams to:
• Optimize power grid architecture
• Define power strap requirements
• Guide placement constraints to improve power integrity
• Support ECOs to fix IR/EM violations.Tool & Flow Development
• Develop and maintain automated scripts for IR/EM analysis and reporting.