IP Verification Engineer - GPU Core Pipeline

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.

The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”

What you’ll be doing:

As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.

You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.

You will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify.

Work with HW architects and designers to make the right implementation choices.

You will be working with architects, designers, and other members of your verification teams to accomplish your tasks.

What we need to see:

B.Tech./ M.Tech. with 2+ years of relevant experience

Familiarity with Verilog, C++ and OOPs concepts.

Experience in verification and test planning at Unit level.

Experience in developing and working in functional coverage based constrained random verification environments

Good understanding of computer architecture concepts.