IP Logic Design Engineer

Job Details:Job Description: The Role and Impact: As an IP Logic Design Engineer, you will play a pivotal role in driving Intel's innovation by developing cutting-edge logic designs for high-performance IPs integrated into SoC products. Your contributions will directly impact Intel's ability to deliver world-class products across Client, Graphics, and Data Center markets. In this role, you will collaborate with cross-functional teams to define architectures, optimize logic, and ensure the seamless integration of IPs into the broader chip design. This position offers a unique opportunity to shape the future of digital design while leveraging your technical expertise to deliver reliable, power-efficient, and high-quality IP solutions.

Key Responsibilities

• Own and deliver logic design and RTL implementation for IP development, ensuring sign-off verification for functionality, reliability, and synthesis checks.
• Develop architecture and microarchitecture specifications for logic components, driving area, power, and performance optimizations.
• Apply advanced strategies and tools for RTL coding, simulation, and debug, ensuring designs meet power-performance-area (PPA) goals and timing integrity.
• Collaborate with verification teams to review and execute verification plans, resolve failing RTL tests, and implement corrective measures to ensure design feature correctness.
• Support SoC integration efforts, ensuring high-quality IP handoffs and seamless integration into full-chip designs.
• Drive post-silicon validation, debug, and high-volume manufacturing support for IPs.
• Manage stakeholder relationships across logic verification, digital backend, and SoC teams, ensuring alignment on implementation and design objectives.Qualifications:Minimum Qualifications:
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 6+ years of experience in logic design and RTL development.
• Expertise in System Verilog and RTL coding, including advanced digital design techniques.
• Demonstrated experience in clock domain crossing, debugging microarchitecture/simulation, and static timing analysis.
• Proficiency in low-power design strategies, including clock gating and UPF methodologies.
• Familiarity with tools and techniques such as LINT, CDC, RDC, timing/synthesis, and regression/code coverage.
• Strong analytical skills and hands-on experience resolving pre-silicon and post-silicon design challenges.

Preferred Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, or a related field, with 5+ years of relevant experience.