Engineer 1
SiFive
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
About the Role:
As an Engineer I in the Hardware Engineering (DV) group, you will be part of a world-class team verifying complex CPU pipelines and memory subsystems. Your primary focus will be ensuring the architectural and microarchitectural correctness of the Memory Management Unit (MMU). This is an excellent opportunity for a recent graduate or early-career engineer to build deep expertise in advanced CPU verification and RISC-V architecture.
Key Responsibilities:
- MMU Verification: Participate in block-level and subsystem-level verification of the MMU, including TLBs (Translation Lookaside Buffers), page table walkers, and memory protection mechanisms.
- Test Authoring: Write, execute, and debug directed and random test cases to verify complex architectural scenarios and edge cases.
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