DFT Lead

Job Requirements

• Hands on Technical lead with SoC & Netlist level DFT execution experience and one can guide juniors

• Scan Insertion: Stitching every flop in the design into shift registers (scan chains) to set the chip to any state and observe any state.

• ATPG (Automatic Test Pattern Generation): Running tools to generate patterns that detect manufacturing defects via the scan chains.

-