Design Verification Engineer, TPU, Silicon, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 4 years of experience in verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.

• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

• Experience in verification and debug of IP/subsystem/SoCs in the networking domain such as packet processing, bandwidth management, congestion control.

Preferred qualifications:

• Master's degree in Electrical Engineering or a related field.

• Experience with industry-standard simulators, revision control systems, and regression systems.

• Experience in Artificial Intelligence/Machine Learning (AI/ML) accelerators or vector processing units.

• Experience with the full verification life cycle.

• Excellent problem-solving and communication skills.