Design Verification Engineer III, Multimedia, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.

• 4 years of experience verifying digital logic at RTL using SystemVerilog for ASICs.

• Experience coding in SystemVerilog and using standard verification methodologies (i.e., UVM).

• Experience verifying digital IP or subsystems.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering or Computer Science.

• Experience verifying multimedia or image processing hardware components, specifically Image Signal Processors (ISPs), Display Processing Units (DPUs), display interfaces, or Video CODECs.

• Experience with high-speed bus protocols (e.g., AXI, AHB) and memory subsystems.

• Experience with formal verification (SystemVerilog Assertions (SVA)) or emulation platforms (e.g., Palladium, ZeBu).

• Excellent scripting skills (Python, Perl, or Shell) for automation of verification flows.

• Excellent problem-solving, communication, and collaboration skills.