CPU RTL Design Engineer III

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 4 years of professional experience in ASIC/SoC digital design using SystemVerilog.

• Experience working on multi-stage, high-performance CPU pipelines and optimizing them for area, power, and timing.

• Experience in logic design through coursework or industry experience.

• Experience with RISC-V architecture and ISA extensions.

• Experience with micro-architecture and RTL design experience in one CPU pipeline stage (e.g., Instruction Fetch Unit (IFU), Decode/Issue/Execution units, or Load-Store Unit (LSU)).

Preferred qualifications:

• Master’s or PhD degree in Electrical Engineering or Computer Science.

• Experience with modern processor microarchitecture and related technologies and algorithms, through academic projects or industry experience.

• Knowledge of programming languages, such as C, C++, and Python.

• Knowledge of general purpose operating systems, such as Linux or Android.