As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
As part of complex out‑of‑order (OOO) CPU cores verification, we are looking for the role, where you will own verification strategy, methodology, and execution for major core blocks, drive coverage and sign‑off, and act as a technical leader and mentor within the DV team.
Education & Experience:
5+ Years of experience with Bachelor's or Master's in Engineering
- Memory ordering and coherence violations across cores and caches.
- TLB/MMU and privilege/protection corner cases.
-
Work closely with:
- Micro‑architecture and RTL teams to refine designs for correctness and verifiability.
- Performance/modeling teams to align micro‑arch behavior with models and performance targets.
- Post‑silicon teams to reproduce and root‑cause silicon issues in pre‑silicon DV.
Mentoring & Influence
- Mentor junior and mid‑level DV engineers in:
- OOO micro‑architecture concepts and debug.
- Testbench design, stimulus generation, coverage, and methodology.
-
Provide technical leadership across projects:
- Lead DV design and reviews, contribute to architecture/micro‑architecture reviews from a verification perspective.
- Champion best practices in DV and help set technical direction for core verification.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in: India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Similar roles you might like
More openings like this one — take a look before you go.
