Coherent NoC IP Design Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.

• Experience designing high-speed Network-on-Chip (NoC) or fabric IP, including mesh, ring, or torus topologies.

• Experience with Verilog and SystemVerilog for RTL design and synthesis.

• Experience delivering silicon IP blocks through multiple tape-outs.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science.

• Experience with automated NoC generation tools and custom logic design for low-power arbitration and congestion management.

• Expertise in clock domain crossing (CDC) in massive, multi-synchronous fabric environments and working knowledge of Python, Perl, or Tcl for developing design automation scripts and productivity tools.

• Knowledge of on-chip interconnect protocols such as AMBA 5 CHI, AXI5, and ACE.

• Deep understanding of cache coherency protocols (MESI/MOESI) and their hardware implementation within a fabric.

• Ability to work in the trenches with Verification teams to define coverage plans and debug complex testbench failures.