ASIC RTL Engineer III, Silicon, IP Subsystem

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.

• 3 years of experience in ASIC design flows and methodologies, IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design.

• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.

• Experience working on memory controller/direct memory access (DMA).

• Experience with industry standard ASIC design tools for RTL lint, VCS, Verdi.

• Experience in AI accelerator design, data-path design.

• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.