ASIC Emulation Engineer / Technical Leader

Define, design and develop emulation environments needed for complex, large scale networking ASICs. Develop the emulation env, build netlists and use the same to speed up the development cycle and find potential ASIC issues during pre-silicon phase • Work with leading emulation vendors to troubleshoot issues.

What You’ll Do:

Develop state-of-the-art emulation environments that will be used to evaluate the performance and functionality of multi-terabit systems

• Developing emulation infrastructure using C/C++ and TCL, Python etc

• Developing and testing various emulation flows and contributing to different aspect of ASIC verification for bug free Silicon

• Collaborate closely with the design team and the hardware team to verify the ASIC in emulation and during ASIC bring up

• Work closely with the design, DV, power, and post-silicon diagnostic teams

• Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process

• Develop tests to generate complex traffic, performance scenarios to catch potential post Silicon issues during Pre-Silicon phase.

Minimum Qualifications:

- Bachelors + 8 years of related experience, or Masters + 6 years of related experience.

- Design Emulation background with hands-on experience with emulation platforms like Veloce/Palladium/Zebu as well as experience with compilation, debug, performance testing

- Fluent in System Verilog or Verilog to work on the Emulation infrastructure development work

- In-depth knowledge of C/C++, scripting, as well as ASIC design and verification flow

- Expertise in RTL development for Emulation prototypes

- System debug experience using tools like gdb, waveform debuggers.