ASIC Design for Testability Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Building Engineering, Electrical and Electronics Engineering, Controls, IT, or equivalent practical experience.

• 4 years of experience in DFT/DFD flows and methodologies.

• Experience with Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test